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W9412G6IH
9.5
DC Characteristics
SYM.
PARAMETER
-4
MAX.
-5/-5I
-6/-6I
UNIT
NOTES
Operating current: One Bank Active-Precharge;
I DD0
t RC = t RC min; t CK = t CK min;
DQ, DM and DQS inputs changing once per clock cycle;
130
130
120
7
Address and control inputs changing once every two clock cycles.
Operating current: One Bank Active-Read-Precharge;
I DD1
Burst = 4; t RC = t RC min; CL = 3; t CK = t CK min; I OUT = 0 mA;
140
140
130
7, 9
Address and control inputs changing once per clock cycle .
Precharge Power Down standby current:
I DD2P
All Banks Idle; Power down mode;
20
20
20
CKE < V IL max; t CK = t CK min; Vin = V REF for DQ, DQS and DM .
Idle standby current:
I DD2N
CS > V IH min; All Banks Idle; CKE > V IH min; t CK = t CK min;
Address and other control inputs changing once per clock cycle;
45
45
45
7
Vin > V IH min or Vin < V IL max for DQ, DQS and DM .
Active Power Down standby current:
I DD3P
One Bank Active; Power down mode;
CKE < V IL max; t CK = t CK min;
20
20
20
Vin = V REF for DQ, DQS and DM .
Active standby current:
CS > V IH min; CKE > V IH min; One Bank Active-Precharge;
mA
I DD3N
t RC = t RAS max; t CK = t CK min;
60
60
60
7
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle .
Operating current:
I DD4R
Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
185
180
170
7, 9
CL=2; t CK = t CK min; I OUT = 0mA.
Operating current:
Burst = 2; Write; Continuous burst; One Bank Active;
I DD4W
Address and control inputs changing once per clock cycle;
185
180
170
7
CL = 2; t CK = t CK min;
DQ, DM and DQS inputs changing twice per clock cycle.
I DD5
I DD6
Auto Refresh current: t RC = t RFC min.
Self Refresh current: CKE < 0.2V; external clock on; t CK = t CK min.
200
3
200
3
190
3
7
Random Read current: 4 Banks Active Read with activate every
20nS, Auto-Precharge Read every 20 nS;
I DD7
Burst = 4; t RCD = 3; I OUT = 0mA;
DQ, DM and DQS inputs changing twice per clock cycle;
320
320
300
Address changing once per clock cycle.
Publication Release Date: Sep. 16, 2009
- 25 -
Revision A06
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